Samsung develops 12nm-class DDR5 memory

Samsung announced on 21 December that it has developed 16-gigabit DDR5 memory using a 12nm-class process and completed compatibility evaluation with AMD. The chip targets computing, data centres and AI systems.

The company claims up to 23% lower power consumption than its previous DRAM and 20% higher wafer productivity. These are manufacturer figures; application-level gains will depend on the finished system.

Mass production is scheduled for 2023. Development and platform evaluation establish a step towards supply, rather than memory already shipping at scale. Buyers still need production parts and system-level validation before treating the stated efficiency gains as deployment results.

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